The invention relates to a counter and/or divider arrangement, comprising at least two subsidiary counter circuits, each of which comprises a total number of flipflops which are concatenated in respect of their dam inputs and outputs, all subsidiary counter circuits receiving a common clock signal, and also comprising at least one logic element.
German Patent Application P 42 14 612.7 describes an arrangement comprising three frequency divider circuits whose clock inputs are connected together to a terminal carrying a clock signal whose frequency is to be divided. Each of the frequency divider circuits comprises a concatenation of flipflops. An output of the respective last flipflop of each concatenation is connected to a respective input of an AND-gate. From the signals on the outputs of the flipflops, the AND-gate forms a frequency-divided output signal by performing an AND-function, which output signal is determined according to the principle of the smallest common multiples of the division ratios of the individual frequency divider circuits. The resultant division ratio thus stems from the product of the division ratios of the individual frequency divider circuits. The division ratios of the individual frequency divider circuits should not exhibit common prime factors.
In the arrangement described in German Patent Application P 42 14 612.7 suitable interference suppression is achieved because of the construction of the individual frequency divider circuits in which only a few, mutually compensating switching operations take place simultaneously, or in which always at least, substantially the same number of switching operations take place. However, the division ratios that can be achieved in such an arrangement are limited to values which can be formed by the smallest common multiples of the division ratios of the individual frequency divider circuits. For the implementation of frequency division ratios which correspond to large prime numbers or contain such large prime numbers, the described arrangement cannot be used, or leads to unacceptable expenditures.
It is an object of the invention to construct a counter and/or divider arrangement of the kind set forth so that arbitrary counting operations or division ratios can be achieved while maintaining a construction which produces very little switching interference and without excessive expenditures.
In a counter and/or divider arrangement of the kind set forth this object is achieved in that in each logic element signals from the data output of one of the flipflops of at least a part of the subsidiary counter circuits are combined according to an AND-function so as to form an associated resultant signal, each of the resultant signals being applied as a reset signal to at least one of the subsidiary counter circuits in order to adjust the subsidiary counter circuit to an initial state, from at least one of the resultant signals there being formed an output signal, the product of the total numbers of the flipflops of all subsidiary counter circuits being chosen to be greater than or equal to a predetermined maximum count or division ratio, the total numbers being determined so that they do not exhibit common prime factors, the data outputs of the flipflops of the subsidiary counter circuits which are connected to the logic elements being chosen so that the output signal exhibits the predetermined maximum count or division ratio.